1. Technical Field
The present invention relates generally to VLSI design, and more particularly relates to a system and method for testing optical proximity correction algorithms for VLSI design.
2. Related Art
Optical lithography for very large scale integrated (VLSI) circuits is implemented by exposing resist on wafers in a pattern defined by designed shapes on a mask. However, the patterns produced on the wafer normally differ from those designed due to pattern dependent optical distortions when exposure wavelengths are greater than the feature line width. A variety of resolution enhancement techniques, including optical proximity correction (OPC) algorithms, have been devised to compensate for this effect. These OPC algorithms modify the designed layouts in ways so that the actual wafer layout more closely matches the original ideal layout. However, while such OPC algorithms may work for most layouts, they may fail or produce faulty layouts for certain inputted patterns.
To determine whether or not an inputted pattern will cause a faulty result, results can be modeled in software, and analyzed to determine if a faulty layout will occur. However, in order to effectively test an OPC algorithm, a wide variety of patterns must be tested. One problem that arises then is how to create an optimal set of patterns for this testing.
Conventional approaches to test programs include either a collection of actual designs that are used as a test suite, or synthesizing pseudo-random layouts. For the latter technique, a small seed layout is constructed, and variations are produced by making random copies, translations and orientation changes. In both approaches, however, it is unknown how effectively the layout covers the space of possible shape interactions that may reveal flaws in the OPC algorithm. Accordingly, a need exists for efficiently generating a set of test patterns to test OPC algorithms.